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CAT9555
16-bit IC and SMBus I/O Port with Interrupt
FEATURES
400kHz IC bus compatible 2.3V to 5.5V operation Low stand-by current 5V tolerant I/Os 16 I/O pins that default to inputs at power-up High drive capability Individual I/O configuration Polarity inversion register Active low interrupt output Internal power-on reset No glitch on power-up Noise filter on SDA/SCL inputs Cascadable up to 8 devices Industrial temperature range RoHS-compliant 24-lead SOIC and TSSOP, and 24-pad TQFN (4 x 4mm) packages
DESCRIPTION
The CAT9555 is a CMOS device that provides 16-bit parallel input/output port expansion for IC and SMBus compatible applications. These I/O expanders provide a simple solution in applications where additional I/Os are needed: sensors, power switches, LEDs, pushbuttons, and fans. The CAT9555 consists of two 8-bit Configuration ports (input or output), Input, Output and Polarity inversion registers, and an IC/SMBus-compatible serial interface. Any of the sixteen I/Os can be configured as an input or output by writing to the configuration register. The system master can invert the CAT9555 input data by writing to the active-high polarity inversion register. The CAT9555 features an active low interrupt output which indicates to the system master that an input state has changed. The three address input pins provide the device's extended addressing capability and allow up to eight devices to share the same bus. The fixed part of the IC slave address is the same as the CAT9554, allowing up to eight of these devices in any combination to be connected on the same bus. For Ordering Information details, see page 16.
APPLICATIONS
White goods (dishwashers, washing machines) Handheld devices (cell phones, PDAs, digital cameras) Data Communications (routers, hubs and servers)
BLOCK DIAGRAM
A0 A1 A2
(1)
I/O1.0 8-BIT INPUT/ OUTPUT PORTS I/O1.1 I/O1.2 I/O1.3 I/O1.4 I/O1.5 I/O1.6 I/O1.7 I/O0.0 8-BIT INPUT/ OUTPUT PORTS I/O0.1 I/O0.2 I/O0.3 I/O0.4 I/O0.5 VINT I/O0.6 I/O0.7 LP FILTER INT
WRITE pulse READ pulse I2C/SMBUS CONTROL SCL SDA INPUT FILTER
WRITE pulse VCC VSS POWER-ON RESET READ pulse
Notes: (1) All I/Os are set to inputs at RESET
(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
1
Doc. No. MD-9003, Rev. I
CAT9555
PIN CONFIGURATION
SOIC (W), TSSOP (Y)
INT 1 A1 2 A2 3 I/O0.0
4 24 VCC 23 SDA 22 SCL 21 A0
TQFN 4 x 4mm (HV6) (Top View)
SDA
20
24 I/O0.0 I/O0.1 1 2 3 4 5 6 7
23
22
21
19 18 A0 17 I/O1.7 16 I/O1.6 15 I/O1.5 14 I/O1.4 13 I/O1.3
I/O0.1 5 I/O0.2 6 I/O0.3 7 I/O0.4 8 I/O0.5 9 I/O0.6 10 I/O0.7 11 Vss 12
20 I/O1.7 19 I/O1.6 18 I/O1.5 17 I/O1.4 16 I/O1.3 15 I/O1.2 14 I/O1.1 13 I/O1.0
I/O0.2 I/O0.3 I/O0.4 I/O0.5
8
9
10
11
12
I/O0.6
I/O0.7
I/O1.0
I/O1.1
PIN DESCRIPTION
SOIC / TSSOP 1 2 3 4-11 12 13-20 21 22 23 24 TQFN 22 23 24 1-8 9 10-17 18 19 20 21 Pin Name INT A1 A2 I/O0.0 - I/O0.7 VSS I/O1.0 - I/O1.7 A0 SCL SDA VCC Function Interrupt Output (open drain) Address Input 1 Address Input 2 I/O Port 0.0 to I/O Port 0.7 Ground I/O Port 1.0 to I/O Port 1.7 Address Input 0 Serial Clock Serial Data Power Supply
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I/O1.2
Vss
SCL
VCC
INT
A2
A1
CAT9555
ABSOLUTE MAXIMUM RATINGS (1)
Parameters VCC with Respect to Ground Voltage on Any Pin with Respect to Ground DC Current on I/O1.0 to I/O1.7, I/O0.0 to I/O0.7 DC Input Current VCC Supply Current VSS Supply Current Package Power Dissipation Capability (TA = 25C) Junction Temperature Storage Temperature Ratings -0.5 to +6.5 -0.5 to +5.5 50 20 160 200 1.0 +150 -65 to +150 Units V V mA mA mA mA W C C
RELIABILITY CHARACTERISTICS
Symbol VZAP(2) ILTH (2) Parameter ESD Susceptibility Latch-up Reference Test Method JEDEC Standard JESD 22 JEDEC JESD78A Min 2000 100 Units Volts mA
Notes: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) This parameter is tested initially and after a design or process change that affects the parameter.
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3
Doc. No. MD-9003, Rev. I
CAT9555
D.C. OPERATING CHARACTERISTICS
VCC = 2.3V to 5.5V; VSS = 0V; TA = -40C to +85C, unless otherwise specified. Symbol Supplies VCC ICC Istbl Istbh VPOR VIL (1) VIH IL CI
(2) (1)
Parameter Supply voltage Supply current Standby current Standby current Power-on reset voltage Low level input voltage High level input voltage Low level output current Leakage current Input capacitance Output capacitance Low level input voltage High level input voltage Input leakage current Low level input voltage High level input voltage
Conditions
Min 2.3
Typ -- 135 1.1 0.75 1.5 -- -- -- -- -- -- -- -- -- -- -- 8 to 20 10 to 24 -- -- -- -- -- -- -- -- -- --
Max 5.5 200 1.5 1 1.65 0.3 x VCC 5.5 -- +1 6 8 0.3 x VCC 5.5 1 0.3 x VCC 5.5 -- -- -- -- -- -- -- -- 1 -100 5 8
Unit V A mA A V V V mA A pF pF V V A V V mA mA V V V V V V A A pF pF
Operating mode; VCC = 5.5V; no load; fSCL = 100kHz Standby mode; VCC = 5.5V; no load; VI = VSS; fSCL = 0kHz; I/O = inputs Standby mode; VCC = 5.5V; no load; VI = VCC; fSCL = 0kHz; I/O = inputs
-- -- -- -- -0.5 0.7 x VCC
No load; VI = VCC or VSS
SCL, SDA, INT
IOL
VOL = 0.4V VI = VCC = VSS VI = VSS VO = VSS
3 1- -- -- -0.5 0.7 x VCC -1 -0.5 0.7 x VCC
CO (2) VIL(1) VIH I/Os VIL VIH IOL
(1)
A0, A1, A2
ILI
Low level output current
VOL = 0.5V; VCC = 2..3V to 5.5V(3) VOL = 0.7V; VCC = 2.3V to 5.5V(3) IOH = -8 mA; VCC = 2.3V(4) IOH = -10 mA; VCC = 2.3V
(4)
8 10 1.8 1.7 2.6 2.5 4.1 4.0 -- -- -- --
VOH
High level output voltage
IOH = -8 mA; VCC = 3.0V
(4) (4) (4) (4)
IOH = -10 mA; VCC = 3.0V IOH = -8 mA; VCC = 4.75V
IOH = -10mA; VCC = 4.75V IIH IIL CI CO
(2) (2)
Input leakage current Input leakage current Input capacitance Output capacitance
VCC = 3.6V; VI = VCC VCC = 5.5V; VI = VSS
Notes: (1) VIL min and VIH max are reference values only and are not tested. (2) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. (3) Each I/Os must be externally limited to a maximum of 25mA and each octal (I/O0.0 to I/O0.7 and I/O1.0 to I/O1.7) must be limited to a maximum current of 100mA for a device total of 200mA. (4) The total current sourced by all I/Os must be limited to 160mA.
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CAT9555
A.C. CHARACTERISTICS
VCC = 2.3V to 5.5V; TA = -40C to +85C, unless otherwise specified. (1) Symbol FSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF
(2) (2)
Parameter Clock Frequency START Condition Hold Time Low Period of SCL Clock High Period of SCL Clock START Condition Setup Time Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time STOP Condition Setup Time Bus Free Time Between STOP and START SCL Low to Data Out Valid Data Out Hold Time Noise Pulse Filtered at SCL and SDA Inputs Parameter Output Data Valid Input Data Setup Time Input Data Hold Time Interrupt Valid Interrupt Reset
Standard I2C Min 4 4.7 4 4.7 0 250 1000 300 4 4.7 3.5 100 100 Max 100
Fast I2C Min 0.6 1.3 0.6 0.6 0 100 300 300 0.6 1.3 0.9 50 100 Min Max 200 100 1 4 4 Max 400
Units kHz s s s s s ns ns ns s s s ns ns Units ns ns s s s
tSU:STO tBUF
(2)
tAA tDH Ti
(2)
Symbol Port Timing tPV tPS tPH tIV tIR
Interrupt Timing
Notes: (1) Test conditions according to "AC Test Conditions" table. (2) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
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Doc. No. MD-9003, Rev. I
CAT9555
A.C. TEST CONDITIONS
Input Rise and Fall time CMOS Input Voltages CMOS Input Reference Voltages Output Reference Voltages Output Load: SDA, INT Output Load: I/Os 10ns 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC 0.5VCC Current Source IOL = 3mA; CL = 100pF Current Source: IOL/IOH = 10mA; CL = 50pF
tF tLOW SCL tSU:STA tHD:STA
tHIGH tLOW
tR
tHD:DAT
tSU:DAT
tSU:STO
SDA IN tAA SDA OUT tDH tBUF
Figure 1. IC Serial Interface Timing
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CAT9555
PIN DESCRIPTION
SCL: Serial Clock The serial clock input clocks all data transferred into or out of the device. The SCL line requires a pull-up resistor if it is driven by an open drain output. SDA: Serial Data/Address The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. A pullup resistor must be connected from SDA line to VCC. The value of the pull-up resistor, RP, can be calculated based on minimum and maximum values from Figure 2 and Figure 3 (see Note). A0, A1, A2: Device Address Inputs These inputs are used for extended addressing capability. The A0, A1, A2 pins should be hardwired to VCC or VSS. When hardwired, up to eight CAT9555s may be addressed on a single bus system. The levels on these inputs are compared with corresponding bits, A2, A1, A0, from the slave address byte. I/O0.0 to I/O0.7, I/O1.0 to I/O1.7: Input / Output Ports Any of these pins may be configured as input or output. The simplified schematic of I/O0 to I/O7 is shown in Figure 4. When an I/O is configured as an input, the Q1 and Q2 output transistors are off creating a high impedance input with a weak pull-up resistor (typical 100k). If the I/O pin is configured as an output, the push-pull output stage is enabled. Care should be taken if an external voltage is applied to an I/O pin configured as an output due to the low impedance paths that exist between the pin and either VCC or VSS.
IOL = 3mA @ VOLmax
2.5 2 1.5 1 0.5 0 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6 8.00
Fast Mode IC Bus / tr max - 300ns
7.00 6.00 5.00 4.00 3.00 2.00 1.00 0.00 50 100 150 200 250 300 350 400
VCC (V)
RPmax (K)
RPmin (K)
CBUS (pF)
Figure 2. Minimum RP as a Function of Supply Voltage
Figure 3. Maximum RP Value versus Bus Capacitance
Note: According to the Fast Mode IC bus specification, for bus capacitance up to 200pF, the pull up device can be a resistor. For bus loads between 200pF and 400pF, the pull-up device can be a current source (Imax = 3mA) or a switched resistor circuit.
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7
Doc. No. MD-9003, Rev. I
CAT9555 : Interrupt Output INT The open-drain interrupt output is activated when one of the port pins configured as an input changes state (differs from the corresponding input port register bit state). The interrupt is deactivated when the input returns to its previous state or the input port register is read.
Since there are two 8-bit ports that are read independently, the interrupt caused by Port 0 will not be cleared by a read of Port 1, or vice versa. Changing an I/O from an output to an input may cause a false interrupt if the state of the pin does not match the contents of the input port register.
Data from Shift Register Data from Shift Register
Configuration Register D FF Q
Output Port Register Data VCC Q1 100k
Write Configuration Pulse
CK
Q
D FF
Q
I/O Pin Write Pulse CK Q Q2
Output Port Register
Input Port Register
VSS Input Port Register Data
D LATCH Read Pulse CK
Q
Q
To INT
Data from Shift Register Write Polarity Register
D FF CK
Q
Polarity Register Data
Q
Polarity Inversion Register
Figure 4. Simplified Schematic of I/Os
Doc. No. MD-9003 Rev. I
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CAT9555
FUNCTIONAL DESCRIPTION
The CAT9555 general purpose input/output (GPIO) peripheral provides up to sixteen I/O ports, controlled through an IC compatible serial interface The CAT9555 supports the IC Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT9555 operates as a Slave device. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated. IC BUS PROTOCOL The features of the IC bus protocol are defined as follows: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition (Figure 5). START AND STOP CONDITIONS The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT9555 monitors the SDA and SCL lines and will not respond until this condition is met. A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. DEVICE ADDRESSING After the bus Master sends a START condition, a slave address byte is required to enable the CAT9555 for a read or write operation. The four most significant bits of the slave address are fixed as binary 0100 (Figure 6). The CAT9555 uses the next three bits as address bits. The address bits A2, A1 and A0 are used to select which device is accessed from maximum eight devices on the same bus. These bits must compare to their hardwired input pins. The 8th bit following the 7 bit slave address is the R/W bit that specifies whether a read or write operation is to be performed. When this bit is set to "1", a read operation is initiated, and when set to "0", a write operation is selected. Following the START condition and the slave address byte, the CAT9555 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT9555 then performs a read or a write operation depending on the state of the R/W bit.
SCL
SDA START CONDITION STOP CONDITION
Figure 5. START/STOP Condition
SLAVE ADDRESS 0 1 0 0 A2 A1 A0 R/W
FIXED
PROGRAMMABLE HARDWARE SELECTABLE
Figure 6. CAT9555 Slave Address
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Doc. No. MD-9003, Rev. I
CAT9555 ACKNOWLEDGE After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The SDA line remains stable LOW during the HIGH period of the acknowledge related clock pulse (Figure 7). The CAT9555 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each data byte. When the CAT9555 begins a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT9555 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. The master must then issue a stop condition to return the CAT9555 to the standby power mode and place the device in a known state. REGISTERS AND BUS TRANSACTIONS The CAT9555 internal registers and their address and function are shown in Table 1. Table 1. Register Command Byte Command (hex) 0h 1h 2h 3h 4h 5h 6h 7h Register Input Port 0 Input Port 1 Output Port 0 Output Port 1 Polarity Inversion Port 0 Polarity Inversion Port 1 Configuration Port 0 Configuration Port 1 Table 5. Registers 6 and 7 - Configuration Registers bit default bit default C0.7 1 C1.7 1 C0.6 1 C1.6 1 C0.5 1 C1.5 1 C0.4 1 C1.4 1 C0.3 1 C1.3 1 C0.2 1 C1.2 1 C0.1 1 C1.1 1 C0.0 1 C1.0 1 Table 4. Registers 4 and 5 - Polarity Inversion Registers bit default bit default N0.7 0 N1.7 0 N0.6 0 N1.6 0 N0.5 0 N1.5 0 N0.4 0 N1.4 0 N0.3 0 N1.3 0 N0.2 0 N1.2 0 N0.1 0 N1.1 0 N0.0 0 N1.0 0 The command byte is the first byte to follow the device address byte during a write/read bus transaction. The register command byte acts as a pointer to determine which register will be written or read. The input port register is a read only port. It reflects the incoming logic levels of the I/O pins, regardless of whether the pin is defined as an input or an output by the configuration register. Writes to the input port register are ignored. Table 2. Registers 0 and 1 - Input Port Registers bit default bit default I0.7 X I1.7 X I0.6 X I1.6 X I0.5 X I1.5 X I0.4 X I1.4 X I0.3 X I1.3 X I0.2 X I1.2 X I0.1 X I1.1 X I0.0 X I1.0 X
Table 3. Registers 2 and 3 - Output Port Registers bit default bit default O0.7 1 O1.7 1 O0.6 1 O1.6 1 O0.5 1 O1.5 1 O0.4 1 O1.4 1 O0.3 1 O1.3 1 O0.2 1 O1.2 1 O0.1 1 O1.1 1 O0.0 1 O1.0 1
BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START 1 8 9
BUS RELEASE DELAY (RECEIVER)
ACK SETUP ( tSU:DAT) ACK DELAY ( tAA)
Figure 7. Acknowledge Timing
Doc. No. MD-9003 Rev. I
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CAT9555 The output port register sets the outgoing logic levels of the I/O ports, defined as outputs by the configuration register. Bit values in this register have no effect on I/O pins defined as inputs. Reads from the output port register reflect the value that is in the flip-flop controlling the output, not the actual I/O pin value. The polarity inversion register allows the user to invert the polarity of the input port register data. If a bit in this register is set ("1") the corresponding input port data is inverted. If a bit in the polarity inversion register is cleared ("0"), the original input port polarity is retained. The configuration register sets the directions of the ports. Set the bit in the configuration register to enable the corresponding port pin as an input with a high impedance output driver. If a bit in this register is cleared, the corresponding port pin is enabled as an output. At power-up, the I/Os are configured as inputs with a weak pull-up resistor to VCC. Writing to the Port Registers Data is transmitted to the CAT9555 registers using the write mode shown in Figure 8 and Figure 9. The CAT9555 registers are configured to operate at four register pairs: Input Ports, Output Ports, Polarity Inversion Ports and Configuration Ports. After sending data to one register, the next data byte will be sent to the other register in the pair. For example, if the first byte of data is sent to the Configuration Port 1 (register 7), the next byte will be stored in the Configuration Port 0 (register 6). Each 8-bit register may be updated independently of the other registers. Reading the Port Registers The CAT9555 registers are read according to the timing diagrams shown in Figure 10 and Figure 11. Data from the register, defined by the command byte, will be sent serially on the SDA line. Data is clocked into the register on the failing edge of the acknowledge clock pulse. After the first byte is read, additional data bytes may be read, but the second read will reflect the data from the other register in the pair. For example, if the first read is data from Input Port 0, the next read data will be from Input Port 1. The transfer is stopped when the master will not acknowledge the data byte received and issue the STOP condition.
SCL
1
2
3
4
5
6
7
8
9 command byte data to port 0 1 0 A 0.7 DATA 0 0.0 A 1.7 acknowledge from slave data to port 1 DATA 1 1.0 A P stop condition
slave address SDA S 0 1 0 0 A2 A1 A0 0 R/W A 0 0
0
0
0
0
start condition
acknowledge from slave
acknowledge from slave
WRITE TO PORT DATA OUT FROM PORT 0 tpv DATA OUT FROM PORT 1 DATA VALID tpv
Figure 8. Write to Output Port Register
SCL
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
slave address SDA S 0 1 0 0 A2 A1 A0 0 R/W A 0 0
command byte
data to configuration 0 1 0 A MSB acknowledge from slave DATA 0 LSB A MSB
data to configuration 1 DATA 1 LSB A P
0
0
0 A
1
start condition
acknowledge from slave
acknowledge from slave
Figure 9. Write to Configuration Register
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11
Doc. No. MD-9003, Rev. I
CAT9555 POWER-ON RESET OPERATION When the power supply is applied to VCC pin, an internal power-on reset pulse holds the CAT9555 in a reset state until VCC reaches VPOR level. At this point, the reset condition is released and the internal state machine and the CAT9555 registers are initialized to their default state.
slave address
S 0 1 0 0
acknowledge from slave
acknowledge from slave
slave address
0 0 1 0
acknowledge from slave
data from lower or upper byte of register
acknowledge from master
A2 A1 A0
0
A
COMMAND BYTE
A
S
A2 A1 A0
1
A MSB
DATA
LSB
A
R/W at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter
R/W
first byte
data from upper or lower byte of register
MSB DATA
no acknowledge from master
LSB NA P
Note: Transfer can be stopped at any time by a STOP condition. last byte
Figure 10. Read from Register
SCL
1
2
3
4
56
7
8
9 I0.x I1.x A DATA 10 A I0.x DATA 03 A I1.x DATA 12 1 P
SDA
S
0
1
0
0 A2 A1 A0
1
A
DATA 00
R/W ACKNOWLEDGE FROMSLAVE tph READFROMPORT 0 DATA INTO POR 0 T READFROMPORT 1 DATA INTO POR 1 T DATA 10 DATA 00 DATA 01
ACKNOWLEDGE FROMMASTER
ACKNOWLEDGE FROM MASTER tps
ACKNOWLEDGE FROM MASTER NON ACKNOWLEDGE FROM MASTER
DATA 02 tph
DATA 03 tps
DATA 11
DATA 12
INT tIV tIR
Note:
Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte has previously been set to 00 (read input port register).
Figure 11. Read Input Port Register
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(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
CAT9555
PACKAGE OUTLINE DRAWINGS
SOIC 24-Lead 300mils (W)
(1) (2)
SYMBOL
MIN
NOM
MAX
A A1 A2 b
E1 E
2.35 0.10 2.05 0.31 0.20 15.20 10.11 7.34 1.27 BSC 0.25 0.40 0 5
2.65 0.30 2.55 0.51 0.33 15.40 10.51 7.60 0.75 1.27 8 15
c D E E1 e h
b PIN#1 IDENTIFICATION
e
L 1
TOP VIEW
D
h
h
1
A
A2
1
A1 SIDE VIEW
L END VIEW
c
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC standard MS-013
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13
Doc. No. MD-9003, Rev. I
CAT9555
TSSOP 24-Lead 4.4mm (Y)
(1) (2)
b
SYMBOL
MIN
NOM
MAX
A A1 A2 b
E1 E
1.20 0.05 0.80 0.19 0.09 7.70 6.25 4.30 7.80 6.40 4.40 0.65 BSC 1.00 REF 0.50 0 0.60 0.70 8 0.15 1.05 0.30 0.20 7.90 6.55 4.50
c D E E1 e L L1 1
e TOP VIEW
D c A2 A 1 L1 L SIDE VIEW END VIEW
A1
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC standard MO-153.
Doc. No. MD-9003 Rev. I
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(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
CAT9555
TQFN 24-Pad 4 x 4mm (HV6)
(1) (2)
D
A DETAIL A
E
E2
PIN#1 ID PIN#1 INDEX AREA TOP VIEW D2
A1 SIDE VIEW
BOTTOM VIEW
b SYMBOL MIN NOM MAX
e
L
A A1 b D D2 E E2 e L
0.70 0.00 0.20 3.90 2.70 3.90 2.70 0.30
0.75 0.02 0.25 4.00 2.80 4.00 2.80 0.50 BSC 0.40
0.80 0.05 0.30 4.10 2.90 4.10 2.90 0.50
A1 FRONT VIEW A DETAIL A
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC standard MO-220.
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15
Doc. No. MD-9003, Rev. I
CAT9555
EXAMPLE OF ORDERING INFORMATION (1)
Prefix CAT
Optional Company ID
Device # 95554
Product Number
Suffix HV6
Package W: SOIC Y: TSSOP HV6: TQFN
I
-G
Lead Finish Blank: Matte-Tin G: NiPdAu
T2
Tape & Reel T: Tape & Reel 1: 1,000/Reel SOIC only 2: 2,000/Reel
9555
Temperature Range I = Industrial (-40C to 85C)
ORDERING PART NUMBER
Part Number CAT9555WI CAT9555WI-T1 CAT9555YI CAT9555YI-T2 CAT9555HV6I-G CAT9555HV6I-GT2 Package SOIC SOIC TSSOP TSSOP TQFN TQFN Lead Finish Matte-Tin Matte-Tin Matte-Tin Matte-Tin NiPdAu NiPdAu
For Product Top Mark Codes, click here: http://www.catsemi.com/techsupport/producttopmark.asp
Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is Matte-Tin for SOIC and TSSOP packages and NiPdAu on TQFN package. (3) The device used in the above example is a CAT9555HV6I-GT2 (TQFN, Industrial Temperature, NiPdAu, Tape & Reel, 2,000/Reel). (4) For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
Doc. No. MD-9003 Rev. I
16
(c) 2008 SCILLC. All rights reserved Characteristics subject to change without notice
CAT9555
REVISION HISTORY
Date 09-Dec-04 07-Jan-05 11-Mar-05 25-Sep-06 12-Mar-07 07-Jun-07 21-Jan-08 Revision A B C D E F G Description Advance Information - Initial Issue Advance Information - Minor changes Advance Information - Edit Features - Edit Ordering Information Initial Release Update Ordering Information: Tape and Reel for SOIC package Update Figure 6 Add NiPdAu lead finish for TQFN package Update Example of Ordering Information Update Package Outline Drawings Change document number from 8551 Delete TQFN package in Matte-Tin Update Package Outline Drawings - TQFN 24-Pad 4 x 4mm Update A.C. Characteristics table to include Standard I2C and Fast I2C. Change logo and fine print to ON Semiconductor
05-May-08 01-Dec-08
H I
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center: Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
(c) Catalyst Semiconductor, Inc. Characteristics subject to change without notice
17
Doc. No. MD-9003, Rev. I

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